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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 257
Jul 04, 2013
Figure 6-54. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0)
TSmn
TEmn
TImn
TDRmn
TCRmn
0000H
c
b
0000H
a
c
d
INTTMmn
FFFFH
ba
d
OVF
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output
pin (TOmn) : n = 0, 1, 3 to 7))
2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TImn: TImn pin input signal
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
OVF: Bit 0 of timer status register mn (TSRmn)