RL78/G1A CHAPTER 19 RESET FUNCTION
The status of the RESF register when a reset request is generated is shown in Table 19-3.
Table 19-3. RESF Register Status When Reset Request Is Generated
Reset Source
Flag
RESET Input
Reset by
POR
Reset by
Execution of
Illegal
Instruction
Reset by
WDT
Reset by
RAM Parity
Error
Reset by
Illegal-
memory
Access
Reset by
LVD
TRAP bit Set (1) Held
WDTRF bit Held Set (1) Held
RPERF bit Held Set (1) Held
IAWRF bit Held Set (1) Held
LVIRF bit
Cleared (0)
Held Set (1)
<R>
The RESF register is automatically cleared when it is read by an 8-bit memory manipulation instruction. Figure 19-5
shows the procedure for checking a reset source.
R01UH0305EJ0200 Rev.2.00 747
Jul 04, 2013