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RL78/G1A CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00 370
Jul 04, 2013
Figure 11-15. Conversion Operation of A/D Converter (Software Trigger Mode)
Sampling time
Sampling A/D conversion
Undefined
A/D converter
operation
ADCS ← 1 or ADS rewrite
SAR
ADCR
INTAD
SAR clear
Conversion time
Conversion
result
Conversion
result
In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
In sequential conversion mode, A/D conversion operations proceed continuously until the software clears bit 7 (ADCS)
of the A/D converter mode register 0 (ADM0) to 0.
Rewriting and overwriting to the analog input channel specification register (ADS) during A/D conversion interrupts the
current conversion after which A/D conversion of the analog input specified by the ADS register proceeds. Data from the
A/D conversion that was in progress are discarded.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
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