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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 226
Jul 04, 2013
(2) Operation of event counter mode
<1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0).
<2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data
register mn (TDRmn) is loaded to the TCRmn register to start counting.
<4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the
TImn input.
Figure 6-26. Operation Timing (In Event Counter Mode)
Remarks 1. The timing is shown in Figure 6-24 indicates while the noise filter is not used. By making the noise
filter on-state, the edge detection becomes 2 f
MCK cycles (it sums up to 3 to 4 cycles) later than the
normal cycle of TImn input. The error per one period occurs by the asynchronous between the
period of the TImn input and that of the count clock (f
MCK).
2. m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output
pin (TOmn) : n = 0, 1, 3 to 7))
fMCK
TSmn (Write)
TEmn
TImn input
<1>
<2>
Count clock
Edge detection
Edge detection
<4>
m
TCRmn
Initial
value
m
m−1
m−2
TDRmn
<3>
Start trigger
detection signal
<1>
<3>
<R>