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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 70
Jul 04, 2013
Table 3-5. SFR List (4/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFFA8H Reset control flag register RESF R
− √ −
Undefined
Note 1
FFFA9H Voltage detection register LVIM R/W
√ √ −
00H
Note 1
FFFAAH Voltage detection level register LVIS R/W
√ √ −
00H/01H/81H
Note 1
FFFABH Watchdog timer enable register WDTE R/W
− √ −
1AH/9AH
Note 2
FFFACH CRC input register CRCIN R/W
− √ −
00H
FFFB0H DMA SFR address register 0 DSA0 R/W
− √ −
00H
FFFB1H DMA SFR address register 1 DSA1 R/W
− √ −
00H
FFFB2H DRA0L R/W
− √
00H
FFFB3H
DMA RAM address register 0
DRA0H
DRA0
R/W
− √
√
00H
FFFB4H DRA1L R/W
− √
00H
FFFB5H
DMA RAM address register 1
DRA1H
DRA1
R/W
− √
√
00H
FFFB6H DBC0L R/W
− √
00H
FFFB7H
DMA byte count register 0
DBC0H
DBC0
R/W
− √
√
00H
FFFB8H DBC1L R/W
− √
00H
FFFB9H
DMA byte count register 1
DBC1H
DBC1
R/W
− √
√
00H
FFFBAH DMA mode control register 0 DMC0 R/W
√ √ −
00H
FFFBBH DMA mode control register 1 DMC1 R/W
√ √ −
00H
FFFBCH DMA operation control register 0 DRC0 R/W
√ √ −
00H
FFFBDH DMA operation control register 1 DRC1 R/W
√ √ −
00H
Notes 1. The reset values of the registers vary depending on the reset source as shown below.
Reset Source
Register
RESET Input
Reset by
POR
Reset by
Execution of
Illegal
Instruction
Reset by
WDT
Reset by
RAM parity
error
Reset by
illegal-
memory
access
Reset by
LVD
TRAP Set (1) Held
WDTRF Held Set (1) Held
RPERF Held Set (1) Held
IAWRF Held Set (1)
Held
RESF
LVIRF
Cleared (0)
Held Set (1)
LVISEN Cleared (0)
LVIOMSK
LVIM
LVIF
Held
LVIS Cleared (00H/01H/81H)
Held
2. The reset value of the WDTE register is determined by the setting of the option byte.
<R>
<R>