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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 90
Jul 04, 2013
Figure 3-31. Example of ES:word[B], ES:word[C]
XFFFFH
X0000H
r(B/C)
X0000H
ES
ES: word [B]㧘ES: word [C]
Specifies a
64 KB area
Array of
word-sized
data
Offset
Address of a word within an array
Target memory
Instruction code
<1> <2>
<2>
<3> <3>
<3>
<3>
<1>
<1>
<1>
<2>
<2>
Memory
OP-code
Low Addr.
High Addr
.
The ES register <1> specifies a 64 KB area within the overall
1-Mbyte space as the four higher-order bits, X, of the address range.
“word” <2> specifies the address where the target array of word-sizeddata
starts in the 64 KB area specified in the ES register <1>.
Either register <3> specifies an offset within the array tothe target location
in memory.
Figure 3-32. Example of ES:word[BC]
X0000H
rp(BC)
X0000H
ES
ES: word [BC]
OP-code
Low Addr.
High Addr.
Specifies a
64 KB area
Offset
<3>
<3>
<1>
Instruction code
<1> <2>
<2>
<3>
<1>
<2>
Target memory
Memory
XFFFFH
Array of
word-sized
data
Address of a word within an array
The ES register <1> specifies a 64 KB area within the
overall 1 MB space as the four higher-order bits, X, of
the address range.
“word” <2> specifies the address where the target array of
word-sized data starts in the 64 KB area specified in the
ES register <1>.
A pair of registers <3> specifies an offset within the array
to the target location in memory.