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RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
Figure 14-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator
<R>
f
CLK
MDCH
MDCL
MDSM
DIVMODE
MACMODE
DIVST
INTMD
MDAH
MDAL
MDBH
MDBL
MACSFMACOF
Addition block
Multiplication/division
control register (MDUC)
Counter
Clear
Start
32
Division result
(quotient)
Multiplication/division data register A
Multiplicand
Internal bus
Division
result
(remainder)
Multiply-
accumulation
result
(accumulated)
Multiplication/division data register C
Multiplication result (product) or
multiplication result (product) while in
multiply-accumulator mode
Multiplication/division data register B
Multiplier Dividend
Divisor
Controller
Controller
Multiplication/division block
Controller
Data flow during division
Data flow during multiplication and multiply-accumulation
<R>
Remark f
CLK: CPU/peripheral hardware clock frequency
R01UH0305EJ0200 Rev.2.00 653
Jul 04, 2013