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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 284
Jul 04, 2013
Figure 6-75. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs)
Interrupt signal
(INTTMmn)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CKm0
CKm1
TSmn
Interrupt signal
(INTTMmp)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CKm0
CKm1
TOmp pin
Output
controller
Master channel
(interval timer mode)
Slave channel 1
(one-count mode)
Interrupt signal
(INTTMmq)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CKm0
CKm1
TOmq pin
Output
controller
Slave channel 2
(one-count mode)
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Timer counter
register mp (TCRmp)
Timer data
register mp (TDRmp)
Timer counter
register mq (TCRmq)
Timer data
register mq (TDRmq)
Remark m: Unit number (m = 0), n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7
However, timer output pin (TOmp, TOmq) : p = 1, 3 to 6, q = 3 to 7