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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 74
Jul 04, 2013
Table 3-6. Extended SFR (2nd SFR) List (2/6)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
F007CH Global analog input disable
register
GAIDIS R/W
√ √ −
00H
F007DH Global digital input disable
register
GDIDIS R/W
√ √ −
00H
F0090H Data flash control register DFLCTL R/W
√ √ −
00H
F00A0H High-speed on-chip oscillator
trimming register
HIOTRM R/W
− √ −
Undefined
Note 1
F00A8H High-speed on-chip oscillator
frequency select register
HOCODIV R/W
− √ −
Undefined
Note 2
F00E0H Multiplication/division data
register C (L)
MDCL R/W
− − √
0000H
F00E2H Multiplication/division data
register C (H)
MDCH R/W
− − √
0000H
F00E8H Multiplication/division control
register
MDUC R/W
√ √ −
00H
F00F0H Peripheral enable register 0 PER0 R/W
√ √ −
00H
F00F3H Subsystem clock supply mode
control register
OSMC R/W
− √ −
00H
F00F5H RAM parity error control register RPECTL R/W
√ √ −
00H
F00FEH BCD adjust result register BCDADJ R
− √ −
Undefined
F0100H
SSR00L
− √
F0101H
Serial status register 00
−
SSR00 R
− −
√
0000H
F0102H SSR01L
− √
F0103H
Serial status register 01
−
SSR01 R
− −
√
0000H
F0104H SSR02L
− √
F0105H
Serial status register 02
−
SSR02 R
− −
√
0000H
F0106H SSR03L
− √
F0107H
Serial status register 03
−
SSR03 R
− −
√
0000H
F0108H SIR00L
− √
F0109H
Serial flag clear trigger register
00
−
SIR00 R/W
− −
√
0000H
F010AH SIR01L
− √
F010BH
Serial flag clear trigger register
01
−
SIR01 R/W
− −
√
0000H
F010CH SIR02L
− √
F010DH
Serial flag clear trigger register
02
−
SIR02 R/W
− −
√
0000H
F010EH SIR03L
− √
F010FH
Serial flag clear trigger register
03
−
SIR03 R/W
− −
√
0000H
Notes 1. The value after a reset is adjusted at the time of shipment.
2. The value after a reset is a value set in FRQSEL2 to FRQSEL0 of the option byte (000C2H).
<R>
<R>