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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 253
Jul 04, 2013
Figure 6-50. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1)
TS00
TE00
TI00
TDR00
TCR00
TO00
INTTM00
0002H
Divided
by 6
0001H
0
0000H
1
2
0
1
2
0
1
0
1
0
1
0
1
0
1
2
Divided
by 4
Remark TS00: Bit n of timer channel start register 0 (TS0)
TE00: Bit n of timer channel enable status register 0 (TE0)
TI00: TI00 pin input signal
TCR00: Timer count register 00 (TCR00)
TDR00: Timer data register 00 (TDR00)
TO00: TO00 pin output signal