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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 209
Jul 04, 2013
6.3.7 Timer channel stop register m (TTm)
The TTm register is a trigger register that is used to stop the counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared
to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TEHm1, TEHm3 = 0),
because they are trigger bits.
The TTm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Reset signal generation clears this register to 0000H.
Figure 6-15. Format of Timer Channel Stop register m (TTm)
Address: F01B4H, F01B5H (TT0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTm 0 0 0 0
TTHm
3
0
TTHm
1
0
TTm
7
TTm
6
TTm
5
TTm
4
TTm
3
TTm
2
TTm
1
TTm
0
TTH
m3
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
0 No trigger operation
1 TEHm3 bit clear to 0, to be count operation stop status.
TTH
m1
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
0 No trigger operation
1 TEHm1 bit clear to 0, to be count operation stop status.
TTm
n
Operation stop trigger of channel n
0 No trigger operation
1
TEmn bit clear to 0, to be count operation stop status.
This bit is the trigger to stop operation of the lower 8-bit timer for TTm1 and TTm3 when channel 1 or 3 is in
the 8-bit timer mode.
Caution Be sure to clear bits 15 to 12, 10, 8 of the TTm register to “0”.
Remarks 1. When the TTm register is read, 0 is always read.
2. m: Unit number (m = 0),n: Channel number (n = 0 to 7)