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RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA
Cautions 1. The fastest operation frequency of the IICA operation clock (fMCK) is 20 MHz (Max.).
Set the bit 0 (PRS0) of the IICA control register 01 (IICCTL01) to 1, only when the fCLK exceeds
20 MHz.
2. Note the minimum f
CLK operation frequency when setting the transfer clock.
The minimum fCLK operation frequency for serial interface IICA is determined according to the
mode.
Fast mode: f
CLK = 3.5 MHz (MIN.)
Fast mode plus: fCLK = 10 MHz (MIN.)
Normal mode: fCLK = 1 MHz (MIN.)
Remarks 1. Calculate the rise time (t
R) and fall time (tF) of the SDAA0 and SCLA0 signals separately, because
they differ depending on the pull-up resistance and wire load.
2. IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F: SDAA0 and SCLA0 signal falling times
t
R: SDAA0 and SCLA0 signal rising times
fMCK: IICA operation clock frequency
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R01UH0305EJ0200 Rev.2.00 589
Jul 04, 2013