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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 197
Jul 04, 2013
6.3.1 Peripheral enable register 0 (PER0)
This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-9. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 RTCEN 0 ADCEN IICA0EN
SAU1EN
Note
SAU0EN 0 TAU0EN
TAU0EN Control of timer array 0 unit input clock
0
Stops supply of input clock.
• SFR used by the timer array unit 0 cannot be written.
• The timer array unit 0 is in the reset status.
1
Supplies input clock.
• SFR used by the timer array unit 0 can be read/written.
Notes 32, 48, and 64-pin products only.
Cautions 1. When setting the timer array unit, be sure to set the TAUmEN bit to 1 first. If TAUmEN = 0,
writing to a control register of timer array unit is ignored, and all read values are default
values (except for the timer input select register 0 (TIS0), input switch control register
(ISC), noise filter enable register 1 (NFEN1), port mode control registers 0, 1, 3, 4 (PMC0,
PMC1, PMC3, PMC4), port mode registers 0, 1, 3, 4 (PM0, PM1, PM3, PM4), and port
registers 0, 1, 3, 4 (P0, P1, P3, P4)).
• Timer clock select register m (TPSm)
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
2. Be sure to clear the following bits to 0.
25-pin products: bits 1, 3, 6
32, 48, 64-pin products: bits 1, 6
<R>
<R>