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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 89
Jul 04, 2013
Figure 3-29. Example of word[BC]
FFFFFH
F0000H
rp(BC)
word [BC]
OP-code
Low Addr.
High Addr.
Instruction code
Address of a word
within an array
Offset
Array of
word-sized
data
“word” <1> specifies the address where the target
array of word-sized data starts in the 64 KB area
from F0000H to FFFFFH.
A pair of registers <2> specifies an offset within
the array to the target location in memory.
Target memory
Memory
<1>
<1>
<1> <2>
<2>
<2>
Figure 3-30. Example of ES:[HL + byte], ES:[DE + byte]
XFFFFH
X0000H
rp(HL/DE)
X0000H
ES
ES: [HL + byte]㧘ES: [DE + byte]
Target
array
of data
Address of
an array
OP-code
byte
<3>
Specifies a
64 KB area
Offset
<3>
<1>
Instruction code
<1> <2> <3> <3><1>
<1>
<2>
<2>
<2>
Target memory
Memory
Other data in
the array
The ES register <1> specifies a 64 KB
area within the overall 1 MB space as
the four higher-order bits, X, of the address range.
Either pair of registers <2> specifies the address
where the target array of data starts in the 64 KB
area specified in the ES register <1>.
“byte” <3> specifies an offset within the array to the
target location in memory.