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RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) Operation
(2 × 3 + (−4) = 2 → 32767 × (−1) + (−2147483647) = −2147450882 (overflow occurs.))
<1>
<3> <3>
<3> <3>
<2> <5> <6><4>
00H
MDCH
0000H 8000H
7FFFH
MDUC
MDSM
L
<7> <8> <2> <5> <6><4> <7> <8>
<10>, <11>
<12>
<9>
48H
0000H FFFFH
MDCL
8002H
0000H FFFCH 0002H 0001H
MDAL 0000H 0002H 7FFFH
MDAH
INTMD
0000H 0003H FFFFH
MDBH
MDBL
MACOF
MACSF
L
4AH 48H 4AH
Operation clock
4CH
0000H
0000H
0000H
0006H
FFFFH
8001H
<9>
<R>
R01UH0305EJ0200 Rev.2.00 665
Jul 04, 2013