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RL78/G1A CHAPTER 19 RESET FUNCTION
Notes 1. When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummy-
output as a reset signal to an external device, because P130 outputs a low level when reset is effected. To
release a reset signal to an external device, set P130 to high-level output by software.
2. Reset times (times for release from the external reset state)
After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use.
0.399 ms (typ.), 0.519 ms (max.) when the LVD is off.
After the second release of the POR: 0.531 ms (typ.), 0.675 ms (max.) when the LVD is in use.
0.259 ms (typ.), 0.362 ms (max.) when the LVD is off.
After power is supplied, a voltage stabilization waiting time of about 0.99 ms (typ.) and up to 2.30 ms (max.)
is required before reset processing starts after release of the external reset.
3. The state of P40 is as follows.
<R>
• High-impedance during the external reset period or reset period by the POR.
• High level during other types of reset or after receiving a reset signal (connected to the internal pull-up
resistor).
<R>
Caution The watchdog timer is also reset without exception.
Reset by POR and LVD circuit supply voltage detection is automatically released when V
DD ≥ VPOR or VDD ≥ VLVD after
the reset. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating
clock starts. For details, see CHAPTER 20 POWER-ON-RESET CIRCUIT or CHAPTER 21 VOLTAGE DETECTOR.
Remark V
POR: POR power supply rise detection voltage
V
LVD: LVD detection voltage
R01UH0305EJ0200 Rev.2.00 743
Jul 04, 2013