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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 562
Jul 04, 2013
12.8.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 12-113. Timing Chart of Stop Condition Generation
Stop condition
STmn
SEmn
SOEmn
SCLr output
SDAr output
Operation
stop
SOmn
bit manipulation
CKOmn
bit manipulation
SOmn
bit manipulation
Note
Note During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before
receiving the last data.
Figure 12-114. Flowchart of Stop Condition Generation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21),
mn = 00 to 03, 10, 11
Starting generation of stop condition.
End of IIC communication
Writing 1 to the STmn bit to clear
(the SEmn bit is cleared to 0)
Writing 0 to the SOEmn bit
Writing 1 to the SOmn bit
Writing 1 to the CKOmn bit
Writing 0 to the SOmn bit
Completion of data
transmission/data reception
Wait
Secure a wait time so that the specifications of
I
2
C on the slave side are satisfied.
Operation stop status (operable CKOmn
manipulation)
Operation disable status (operable SOmn
manipulation)
Timing to satisfy the low width standard of SCL
for the I
2
C bus.