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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 512
Jul 04, 2013
Figure 12-80. Flowchart of UART Transmission (in Single-Transmission Mode)
Starting UART communication
Write 1 to STmn bit
Transmission completed?
No
Yes
End of commnunication
Writing transmit data to
the SDRmn[7:0] bits
(TXDq register) (8 bits) or
the SDRmn[8:0] bits (9 bits)
When Transfer end interrupt is generated,
it moves to interrupt processing routine
Setting transmit data
For the initial setting, see Figure 12-77.
(Select transfer end interrupt)
SAU default setting
Wait for transmit completes
Transfer end interrupt
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI).
Disable interrupt (MASK)
Set data for transmission and the number of data. Clear communication end flag
(Storage area, transmission data pointer, number of communication data and
communication end flag are optionally set on the internal RAM by the software)
Check completion of transmission by
verifying transmit end flag
Transmission starts by writing
to the SDRmn[7:0] bits.
Read transmit data from storage area and write it
to TxDq. Update transmit data pointer.
Read transmit data, if any, from storage area and
write it to TxDq. Update transmit data pointer.
If not, set transmit end flag
Main routine
Interrupt processing routine
Transmitting next data?
Writing transmit data to the
SDRmn[7:0] bits
(TXDq register) (8 bits) or
the SDRmn[8:0] bits (9 bits)
No
Sets communication
completion flag
RETI
Yes
Main routine
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 2)
mn = 00, 02, 10
<R>
<R>
<R>