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RL78/G1A CHAPTER 1 OUTLINE
(2/2)
Jul 04, 2013
25-pin 32-pin 48-pin 64-pin Item
R5F10E8x R5F10EBx R5F10EGx R5F10ELx
1 2 2 2 Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,
2.5 MHz, 5 MHz, 10 MHz
(Main system clock: f
MAIN = 20 MHz operation)
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,
2.5 MHz, 5 MHz, 10 MHz
(Main system clock: f
MAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz,
4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: f
SUB = 32.768 kHz operation)
8/12-bit resolution A/D converter 13 channels 18 channels 24 channels 28 channels
Serial interface [25-pin products]
• CSI: 1 channel/simplified I
2
C: 1 channel/UART: 1 channel
• CSI: 1 channel/simplified I
2
C: 1 channel/UART: 1 channel
[32-pin products]
• CSI: 1 channel/simplified I
2
C: 1 channel/UART: 1 channel
• CSI: 1 channel/simplified I
2
C: 1 channel/UART: 1 channel
• CSI: 1 channel/simplified I
2
C: 1 channel/UART (UART supporting LIN-bus): 1 channel
[48-pin products]
• CSI: 2 channels/simplified I
2
C: 2 channels/UART: 1 channel
• CSI: 1 channel/simplified I
2
C: 1 channel/UART: 1 channel
• CSI: 2 channels/simplified I
2
C: 2 channels/UART (UART supporting LIN-bus): 1 channel
[64-pin products]
• CSI: 2 channels/simplified I
2
C: 2 channels/UART: 1 channel
• CSI: 2 channels/simplified I
2
C: 2 channels/UART: 1 channel
• CSI: 2 channels/simplified I
2
C: 2 channels/UART (UART supporting LIN-bus): 1 channel
I
2
C bus 1 channel 1 channel 1 channel 1 channel
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
Multiplier and divider/multiply-
accumulator
DMA controller 2 channels
Internal 24 27 27 27 Vectored interrupt
sources
External 6 6 10 13
Note 1
Key interrupt 0 ch (4 ch) 1 ch (6 ch)
Note 1
6 ch 10 ch
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Reset
Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.)
• Power-down-reset: 1.50 V (TYP.)
• Rising edge : 1.67 V to 3.14 V (12 stages)
• Falling edge : 1.63 V to 3.06 V (12 stages)
Voltage detector
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 3.6 V
TA = −40 to +85°C (A: Consumer application), TA = −40 to +105°C (G: Industrial application) Operating ambient temperature
Notes 1. Can be used by the Peripheral I/O redirection register (PIOR).
2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
R01UH0305EJ0200 Rev.2.00 18