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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 455
Jul 04, 2013
(4) Processing flow (in continuous reception mode)
Figure 12-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
Dummy data Dummy data
Write
Write
Reception & shift operation
BFFmn
<1>
<2>
Dummy data
Write
MDmn0
Receive data 2
Receive data 1
Receive data 1
Data reception
STmn
Shift
register mn
Read Read
Read
Receive data 2
Receive data 3
Reception & shift operation
Reception & shift operation
Data reception Data reception
<2>
<2>
<8>
<5>
<3> <3> <4> <4><3> <6><7>
Receive data 3
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last receive data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-39 Flowchart of Master Reception
(in Continuous Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21),
mn = 00 to 03, 10, 11
<R>
<R>