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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 418
Jul 04, 2013
12.3.6 Serial flag clear trigger register mn (SIRmn)
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn (SSRmn) is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 12-9. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03), After reset: 0000H R/W
F0148H, F0149H (SIR10),F014AH, F014BH (SIR11)
Note 1
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0
FECT
mn
Note 2
PEC
Tmn
OVC
Tmn
FEC
Tmn
Clear trigger of framing error of channel n
0 Not cleared
1 Clears the FEFmn bit of the SSRmn register to 0.
PEC
Tmn
Clear trigger of parity error flag of channel n
0 Not cleared
1 Clears the PEFmn bit of the SSRmn register to 0.
OVC
Tmn
Clear trigger of overrun error flag of channel n
0 Not cleared
1 Clears the OVFmn bit of the SSRmn register to 0.
Notes 1. SIR00 to SIR03: All products
SIR10, SIR11: 32, 48, and 64-pin products
2. The SIR01, SIR03, and SIR11 registers only.
Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR00, SIR02, or SIR10 register) to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the SIRmn register is read, 0000H is always read.
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