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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 528
Jul 04, 2013
Figure 12-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
Setting start
No
Yes
Writing 1 to the STmn bit
→
SEmn = 0
The operation of all channels is also stopped to switch to
the STOP mode.
<1>
<2>
<3>
<4>
<5>
<7>
<6>
Reading receive data from
the SDRmn[7:0] bits (RXDq
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
<9>
<8>
SIRm1 = 0007H
Clear the all error flags
Channel 1 is specified for UART reception.
Change to the UART reception baud rate in SNOOZE mode
(SPSm register and bits 15 to 9 in SDRm1 register).
EOCm1: Make the setting to enable generation of error interrupt INTSREq.
SNOOZE mode setting (make the setting to enable generation
of error interrupt INTSREq in SNOOZE mode).
RxDq edge detected
(Entered the SNOOZE mode)
Normal operation
<7>
Change to the UART
reception baud rate in
normal operation
<10>
<11>
STOP
mode
SNOOZE mode
STOP mode
SNOOZE modeNormal operation
Does TSFmn = 0 on all
channels?
SAU default setting
Setting SSCm register
(SWCm = 1, SSECm = 1)
Writing 1 to the SSmn bit
→
SEmn = 1
Setting interrupt
Entered the STOP mode
INTSRq
Setting SSCm register
(SWCm = 0, SSECm = 0)
Writing 1 to the STm1 bit
Writing 1 to the SSmn bit
Normal operation
Communication wait status
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and set interrupt disable (DI).
f
CLK
supplied to the SAU is stopped.
Clock supply
(UART receive operation)
Reception error detected
If an error occurs, because the CPU switches to
the STOP mode again, the error flag is not set.
RxDq edge detected
(Entered the SNOOZE mode)
Clock supply
(UART receive operation)
Transfer end interrupt (INTSRq) generated
The mode switched from SNOOZE to normal operation.
To operation stop status (SEm1 = 0)
Reset SNOOZE mode setting
Set the SPSm register and bits 15 to 9 in the SDRm1
register.
To communication wait status (SEmn = 1)
(Caution and Remarks are listed on the next page.)
<R>
<R>
<R>