Filter
Top Products
RL78/G1A CHAPTER 28 INSTRUCTION SET
R01UH0305EJ0200 Rev.2.00 844
Jul 04, 2013
Table 28-5. Operation List (12/17)
Notes 1. Number of CPU clocks (f
CLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is
accessed by an 8-bit instruction.
Remarks 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
2. cnt indicates the bit shift count.
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
r 1 1
−
r ← r+1 × ×
!addr16 3 2
−
(addr16) ← (addr16)+1 × ×
ES:!addr16 4 3
−
(ES, addr16) ← (ES, addr16)+1 × ×
saddr 2 2
−
(saddr) ← (saddr)+1 × ×
[HL+byte] 3 2
−
(HL+byte) ← (HL+byte)+1 × ×
INC
ES: [HL+byte]
4 3
−
((ES:HL)+byte) ← ((ES:HL)+byte)+1 × ×
r 1 1
−
r ← r – 1 × ×
!addr16 3 2
−
(addr16) ← (addr16) – 1 × ×
ES:!addr16 4 3
−
(ES, addr16) ← (ES, addr16) – 1 × ×
saddr 2 2
−
(saddr) ← (saddr) – 1 × ×
[HL+byte] 3 2
−
(HL+byte) ← (HL+byte) – 1 × ×
DEC
ES: [HL+byte]
4 3
−
((ES:HL)+byte) ← ((ES:HL)+byte) – 1 × ×
rp 1 1
−
rp ← rp+1
!addr16 3 2
−
(addr16) ← (addr16)+1
ES:!addr16 4 3
−
(ES, addr16) ← (ES, addr16)+1
saddrp 2 2
−
(saddrp) ← (saddrp)+1
[HL+byte] 3 2
−
(HL+byte) ← (HL+byte)+1
INCW
ES: [HL+byte]
4 3
−
((ES:HL)+byte) ← ((ES:HL)+byte)+1
rp 1 1
−
rp ← rp – 1
!addr16 3 2
−
(addr16) ← (addr16) – 1
ES:!addr16 4 3
−
(ES, addr16) ← (ES, addr16) – 1
saddrp 2 2
−
(saddrp) ← (saddrp) – 1
[HL+byte] 3 2
−
(HL+byte) ← (HL+byte) – 1
Increment/
decrement
DECW
ES: [HL+byte]
4 3
−
((ES:HL)+byte) ← ((ES:HL)+byte) – 1
SHR A, cnt 2 1
−
(CY ← A0, Am-1 ← Am, A7 ← 0) ×cnt ×
SHRW AX, cnt 2 1
−
(CY ← AX0, AXm-1 ← AXm, AX15 ← 0) ×cnt ×
A, cnt 2 1
−
(CY ← A7, Am ← Am-1, A0 ← 0) ×cnt ×
B, cnt 2 1
−
(CY ← B7, Bm ← Bm-1, B0 ← 0) ×cnt ×
SHL
C, cnt 2 1
−
(CY ← C
7, Cm ← Cm-1, C0 ← 0) ×cnt ×
AX, cnt 2 1
−
(CY ← AX15, AXm ← AXm-1, AX0 ← 0) ×cnt ×SHLW
BC, cnt 2 1
−
(CY ← BC
15, BCm ← BCm-1, BC0 ← 0) ×cnt ×
SAR A, cnt 2 1
−
(CY ← A0, Am-1 ← Am, A7 ← A7) ×cnt ×
Shift
SARW AX, cnt 2 1
−
(CY ← AX
0, AXm-1 ← AXm, AX15← AX15) ×cnt ×
<R>