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RL78/G1A CHAPTER 18 STANDBY FUNCTION
18.2 Registers Controlling Standby Function
The registers which control the standby function are described below.
• Subsystem clock supply mode control register (OSMC)
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• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For details of registers described above, see CHAPTER 5 CLOCK GENERATOR. For registers which
control the SNOOZE mode, CHAPTER 11 A/D CONVERTER and CHAPTER 12 SERIAL ARRAY UNIT.
18.3 Standby Function Operation
18.3.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, or subsystem clock.
The operating statuses in the HALT mode are shown below.
Caution Because the interrupt request signal is used to clear the HALT mode, if the interrupt mask flag is 0
(the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal
is generated), the HALT mode is not entered even if the HALT instruction is executed in such a
situation.
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R01UH0305EJ0200 Rev.2.00 727
Jul 04, 2013