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RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA
The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 13-33 are explained below.
<3> In the slave device if the address received matches the address (SVA0 value) of a slave device
Note
, that
slave device sends an ACK by hardware to the master device. The ACK is detected by the master device
(ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INTIICA0: end of address transmission) at the falling edge of the 9th
clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLA0 =
0) and issues an interrupt (INTIICA0: address match)
Note
.
<5> The master device changes the timing of the wait status to the 8th clock (WTIM0 = 0).
<6> The slave device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait status
that it set by the slave device.
<7> The master device releases the wait status (WREL0 = 1) and starts transferring data from the slave device
to the master device.
<8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an
interrupt (INTIICA0: end of transfer). Because of ACKE0 = 1 in the master device, the master device then
sends an ACK by hardware to the slave device.
<9> The master device reads the received data and releases the wait status (WREL0 = 1).
<10> The ACK is detected by the slave device (ACKD0 = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and the slave device
issue an interrupt (INTIICA0: end of transfer).
<12> By the slave device writing the data to transmit to the IICA0 register, the wait status set by the slave device
is released. The slave device then starts transferring data to the master device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0
interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICA0
interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark <1> to <19> in Figure 13-33 represent the entire procedure for communicating data using the I
2
C bus.
Figure 13-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 13-33
(2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 13-33 (3) Data ~ data ~
stop condition shows the processing from <8> to <19>.
R01UH0305EJ0200 Rev.2.00 649
Jul 04, 2013