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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 272
Jul 04, 2013
Figure 6-67. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel)
(a) Timer mode register mn (TMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
CKSmn1
1/0
CKSmn0
0
0
CCSmn
0
MAS
TERmn
1
Note
STSmn2
0
STSmn1
0
STSmn0
1/0
CISmn1
1/0
CISmn0
1/0
0
0
MDmn3
1
MDmn2
0
MDmn1
0
MDmn0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects the software trigger start
001B: Selects the TImn pin input valid edge.
Setting of MASTERmn bit (channels 2, 4, 6)
1: Master channel.
Count clock selection
0: Selects operation clock (f
MCK).
Operation clock (f
MCK) selection
00B: Selects CKm0 as operation clock of channels n.
10B: Selects CKm1 as operation clock of channels n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0
0: Stops the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0
0: Sets master channel output mode.
Note TMRm2, TMRm4, TMRm6: MASTERmn = 1
TMRm0: Fixed to 0
Remark m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6)
<R>
<R>