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RL78/G1A CHAPTER 15 DMA CONTROLLER
Figure 15-8. Example of Setting of Consecutively Capturing A/D Conversion Results
Hardware operation
DEN1 = 1
DSA1 = 1EH
DRA1 = FCE0H
DBC1 = 0100H
DMC1 = 21H
DST1 = 1
Starting A/D conversion
DEN1 = 0
RETI
End
INTDMA1 occurs.
DST1 = 0
Note
INTAD occurs.
DMA1 transfer
Start
User program
processing
Note The DST1 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN1 flag is enabled only when DST1 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA1 (INTDMA1), set the DST1 bit to 0 and then the DEN1 bit to 0 (for details,
see 15.5.5 Forced termination by software).
R01UH0305EJ0200 Rev.2.00 680
Jul 04, 2013