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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 524
Jul 04, 2013
(1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1)
Because EOCm1 = 0, an error interrupt (INTSRE0) is not generated even if a communication error occurs
independently of the setting of SSECmn bit. Transfer end interrupt (INTSR0) is generated.
Figure 12-89. Timing Chart of SNOOZE Mode Operation (OCm1 = 0, SSECm = 0/1)
SS01
SE01
SWC0
SSEC0 L
EOC01 L
SDR01
INTSR0
INTSRE0
L
TSF01
<1>
<2>
<3>
<5>
<6> <8>
<7>
<9>
<4>
ST01
RxD0 pin
P
ST
P
SP SP
ST
<10>
<11>
<12>
CPU operation status
Normal operation
STOP mode
SNOOZE mode
Normal operation
Receive data 1
Receive data 2
Receive data 2Receive data 1
Shift operation
Shift operation
Data reception
Data reception
Shift
register 01
Clock request signal
(internal signal)
Read
Note
Note Read the received data when SWCm is 1
Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, set the STm1 bit to 1 (clear the SEm1 bit, and stop the operation).
And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release).
Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-91 Flowchart of SNOOZE Mode
Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0).
2. m = 0; q = 0
<R>