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RL78/G1A CHAPTER 5 CLOCK GENERATOR
R01UH0305EJ0200 Rev.2.00 170
Jul 04, 2013
Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/5)
(4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
CMC Register
Note 1
CSC
Register
CKC
Register
Setting Flag of SFR Register
Status Transition
EXCLK OSCSEL AMPH
OSTS
Register
MSTOP
OSTC Register
MCM0
(B) → (C)
(X1 clock: 1 MHz ≤ fX ≤ 10 MHz)
0 1 0 Note 2 0 Must be checked 1
(B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
0 1 1 Note 2 0 Must be checked 1
(B) → (C)
(external main clock)
1 1
×
Note 2 0 Must not be checked 1
Unnecessary if these registers
are already set
Unnecessary if the CPU is operating with
the high-speed system clock
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
manipulation instruction after reset release.
This setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A = −40 to +85°C), CHAPTER 30 ELECTRICAL
SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS T
A = −40 to + 105°C).
(5) CPU clock changing from high-speed on-chip oscillator clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
CMC Register
Note
CSC
Register
CKC
Register
Setting Flag of SFR Register
Status Transition
EXCLKS OSCSELS AMPHS1, AMPHS0 XTSTOP
Waiting for
Oscillation
Stabilization
CSS
(B) → (D)
(XT1 clock)
0 1 00: Low power consumption
oscillation
01: Normal oscillation
10: Ultra-low power
consumption oscillation
0 Necessary 1
(B) → (D)
(external sub clock)
1 1
×
0 Necessary 1
Unnecessary if these registers
are already set
Unnecessary if the CPU
is operating with the
subsystem clock
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
This setting is not necessary if it has already been set.
Remarks 1. ×: don’t care
2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15.
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