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RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
14.1 Functions of Multiplier and Divider/Multiply-Accumulator
The multiplier and divider/multiply-accumulator has the following functions.
• 16 bits × 16 bits = 32 bits (Unsigned)
• 16 bits × 16 bits = 32 bits (Signed)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Signed)
• 32 bits ÷ 32 bits = 32 bits, 32-bits remainder (Unsigned)
14.2 Configuration of Multiplier and Divider/Multiply-Accumulator
The multiplier and divider/multiply-accumulator consists of the following hardware.
Table 14-1. Configuration of Multiplier and Divider/Multiply-Accumulator
Item Configuration
Registers
Multiplication/division data register A (L) (MDAL)
Multiplication/division data register A (H) (MDAH)
Multiplication/division data register B (L) (MDBL)
Multiplication/division data register B (H) (MDBH)
Multiplication/division data register C (L) (MDCL)
Multiplication/division data register C (H) (MDCH)
Control register Multiplication/division control register (MDUC)
Figure 14-1 shows a block diagram of the multiplier and divider/multiply-accumulator.
R01UH0305EJ0200 Rev.2.00 652
Jul 04, 2013