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RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA
13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers
(1) Setting transfer clock on master side
Transfer clock =
f
MCK
IICWL0 + IICWH0 + fMCK (tR + tF)
At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
IICWL0 =
0.52
Transfer clock
× fMCK
IICWH0 = (
0.48
Transfer clock
− tR − tF) × fMCK
• When the normal mode
IICWL0 =
0.47
Transfer clock
× fMCK
IICWH0 = (
0.53
Transfer clock
− tR − tF) × fMCK
• When the fast mode plus
IICWL0 =
0.50
Transfer clock
× fMCK
IICWH0 = (
0.50
Transfer clock
− tR − tF) × fMCK
(2) Setting IICWL0 and IICWH0 registers on slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWL0 = 1.3
μ
s × fMCK
IICWH0 = (1.2
μ
s − tR − tF) × fMCK
• When the normal mode
IICWL0 = 4.7
μ
s × fMCK
IICWH0 = (5.3
μ
s − tR − tF) × fMCK
• When the fast mode plus
IICWL0 = 0.50
μ
s × fMCK
IICWH0 = (0.50
μ
s − tR − tF) × fMCK
(Caution and Remarks are listed on the next page.)
R01UH0305EJ0200 Rev.2.00 588
Jul 04, 2013