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RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A = −40 to +85°C)
R01UH0305EJ0200 Rev.2.00 878
Jul 04, 2013
(5) During communication at same potential (simplified I
2
C mode) (2/2)
(T
A = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol Conditions
MIN. MAX. MIN. MAX. MIN. MAX.
Unit
2.7 V ≤ EVDD0 ≤ 3.6 V,
C
b = 50 pF, Rb = 2.7 kΩ
0 305 0 305 0 305 ns
1.8 V ≤ EVDD0 ≤ 3.6 V,
C
b = 100 pF, Rb = 3 kΩ
0 355 0 355 0 355 ns
1.8 V ≤ EVDD0 < 2.7 V,
C
b = 100 pF, Rb = 5 kΩ
0 405 0 405 0 405 ns
1.7 V ≤ EVDD0 ≤ 1.8 V,
C
b = 100 pF, Rb = 5 kΩ
0 405 0 405 0 405 ns
Data hold time (transmission) tHD:DAT
1.6 V ≤ EV
DD0 < 1.8 V,
C
b = 100 pF, Rb = 5 kΩ
− −
0 405 0 405 ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. The value must also be f
CLK/4 or lower.
5. Set the f
MCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (V
DD tolerance (When 25- to 48-pin
products)/EV
DD tolerance (When 64-pin products)) mode for the SDAr pin and the normal output mode
for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).
Simplified I
2
C mode mode connection diagram (during communication at same potential)
RL78
microcontroller
SDAr
SCLr
SDA
SCL
User device
V
DD
R
b
Simplified I
2
C mode serial transfer timing (during communication at same potential)
SDAr
t
LOW
tHIGH
tHD : DAT
SCLr
t
SU : DAT
1/fSCL
Remarks 1. R
b[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01, 10, 11, 20, 21), g: PIM number (g = 0, 1), h: POM number (h = 0, 1)
3. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number, mn = 00 to 03, 10, 11)