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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 407
Jul 04, 2013
12.2.1 Shift register
This is a 9-bit register that converts parallel data into serial data or vice versa.
In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used
Note 1
.
The shift register cannot be directly manipulated by program.
During reception, it converts data input to the serial pin into parallel data, and stores to the lower 8/9 bits of the SDRmn
register.
When data is transmitted, the value transferred from the lower 8/9 bits of the SDRmn register to this register is output
as serial data from the serial output pin.
For details, see 12.2.2 Lower 8/9 bits of the serial data register mn (SDRmn).
8 7 6 5 4 3 2 1 0
Shift register
12.2.2 Lower 8/9 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
Bits 8 to 0 of SDR00, SDR01 (lower 9 bits) or bits 7 to 0 of SDR02, SDR03, SDR10
Note 1
, and SDR11
Note 1
(lower 8 bits)
function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as a register that sets the division
ratio of the operation clock (f
MCK).
Remark For the function of the higher 7 bits of the SDRmn register, see 12.3.5 Higher 7 bits of the serial data
register mn (SDRmn).
When data is received, parallel data converted by the shift register is stored in the lower 8/9 bits. When data is to be
transmitted, set transmit to be transferred to the shift register to the lower 8/9 bits.
The data stored in the lower 8/9 bits of this register is as follows, depending on the setting of bits 0 and 1 (DLSmn0,
DLSmn1) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data.
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
• 9-bit data length (stored in bits 0 to 8 of SDRmn register)
Note 1
The lower 8/9 bits of the SDRmn register can be read or written
Note 2
in 8-bit units as the following SFR, depending on
the communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IICr communication … SIOr (IICr data register)
The SDRmn register can be read or written in 16-bit units.
Reset signal generation clears the SDRmn register to 0000H.
Notes 1. Only following UART0 can be specified for the 9-bit data length.
2. Writing in 8-bit units is prohibited when the operation is stopped (SEmn = 0).
Remarks 1. After data is received, “0” is stored in bits 0 to 8 in bit portions that exceed the data length.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21),
q: UART number (q = 0 to 2), r: IIC number (r = 00, 01, 10, 11, 20, 21)
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