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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 69
Jul 04, 2013
Table 3-5. SFR List (3/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF90H
FFF91H
Interval timer control register ITMC R/W
− − √
0FFFH
FFF92H Second count register SEC R/W
− √ −
00H
FFF93H Minute count register MIN R/W
− √ −
00H
FFF94H Hour count register HOUR R/W
− √ −
12H
Note
FFF95H Week count register WEEK R/W
− √ −
00H
FFF96H Day count register DAY R/W
− √ −
01H
FFF97H Month count register MONTH R/W
− √ −
01H
FFF98H Year count register YEAR R/W
− √ −
00H
FFF99H Watch error correction register SUBCUD R/W
− √ −
00H
FFF9AH Alarm minute register ALARMWM R/W
− √ −
00H
FFF9BH Alarm hour register ALARMWH R/W
− √ −
12H
FFF9CH Alarm week register ALARMWW R/W
− √ −
00H
FFF9DH Real-time clock control register 0 RTCC0 R/W
√ √ −
00H
FFF9EH Real-time clock control register 1 RTCC1 R/W
√ √ −
00H
FFFA0H Clock operation mode control
register
CMC R/W
− √ −
00H
FFFA1H Clock operation status control
register
CSC R/W
√ √ −
C0H
FFFA2H Oscillation stabilization time
counter status register
OSTC R
√ √ −
00H
FFFA3H Oscillation stabilization time
select register
OSTS R/W
− √ −
07H
FFFA4H System clock control register CKC R/W
√ √ −
00H
FFFA5H Clock output select register 0 CKS0 R/W
√ √ −
00H
FFFA6H Clock output select register 1 CKS1 R/W
√ √ −
00H
Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1
after reset.