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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 416
Jul 04, 2013
Caution Be sure to clear bits 3, 6, and 11 to “0”. (Also clear bit 5 of the SCR01, SCR03, or SCR11 register
to 0). Be sure to set bit 2 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21)
12.3.5 Higher 7 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
Bits 8 to 0 (lower 9 bits) of SDR00, SDR01, SDR10, SDR11 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10
Note 1
,
and SDR11
Note 1
function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as a register that
sets the division ratio of the operation clock (f
MCK).
Remark For the function of the lower 8/9 bits of the SDRmn register, see 12.2.2 Lower 8/9 bits of the serial data
register mn (SDRmn).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock by
the bits 15 to 9 (higher 7 bits) of the SDRmn register is used as the transfer clock.
If the CCSmn bit of serial mode register mn (SMRmn) is set to 1, bits 15 to 9 of SDR01, SDR00 (higher 7 bits) are set
to “0000000B”. f
SCK of input clock from the SCKp pin (slave transfer of CSI mode) is the transfer clock.
The higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation (SEmn = 1),
a value is written only to the lower 8/9 bits of the SDRmn register. When the SDRmn register is read during operation, the
higher 7 bits are always read as 0.
The SDRmn register can be read or written in 16-bit units.
Reset signal generation clears the SDRmn register to 0000H.
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