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RL78/G1A CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00 354
Jul 04, 2013
Table 11-3. A/D Conversion Time Selection (3/4)
(3) 8-bit resolution mode (ADTYP = 1) When there is no stabilization wait time
(software trigger mode/hardware trigger no-wait mode)
Conversion Time Selection
A/D Converter Mode Register 0
(ADM0)
AV
DD
= 1.6 to 3.6 V AV
DD
= 1.6 to 3.6 V AV
DD
= 1.8 to 3.6 V AV
DD
= 2.4 to 3.6 V AV
DD
= 2.7 to 3.6 V
FR2 FR1 FR0 LV1 LV0
Mode Conversion
Clock (f
AD)
Number of
Conversion
Clock
Conversion
Time
f
CLK = 1 MHz fCLK = 4 MHz fCLK = 8 MHz fCLK = 16 MHz fCLK = 32 MHz
0 0 0 fCLK/32 1312/fCLK Setting
prohibited
41
μ
s
Note
0 0 1 fCLK/16 656/fCLK
Setting
prohibited
41
μ
s
Note
20.5
μ
s
Note
0 1 0 fCLK/8 328/fCLK 41
μ
s
Note
20.5
μ
s
Note
10.25
μ
s
Note
0 1 1 fCLK/6 246/fCLK 30.75
μ
s
Note
15.375
μ
s
Note
7.6875
μ
s
Note
1 0 0 fCLK/5 205/fCLK
Setting
prohibited
25.625
μ
s
Note
12.8125
μ
s
Note
6.40625
μ
s
Note
1 0 1 fCLK/4 164/fCLK 41
μ
s
Note
20.5
μ
s
Note
10.25
μ
s
Note
5.125
μ
s
Note
1 1 0 fCLK/2 82/fCLK
Setting
prohibited
20.5
μ
s
Note
10.25
μ
s
Note
5.125
μ
s
Note
2.5625
μ
s
Note
1 1 1
0 0 Normal 1
fCLK/1
41 f
AD
(number
of
sampling
clock:
11 f
AD)
41/f
CLK 41
μ
s
Note
10.25
μ
s
Note
5.125
μ
s
Note
2.5625
μ
s
Note
Setting
prohibited
0 0 0 fCLK/32 1696/fCLK Setting
prohibited
53
μ
s
0 0 1 fCLK/16 848/fCLK
Setting
prohibited
53
μ
s 26.5
μ
s
0 1 0 fCLK/8 424/fCLK 53
μ
s
Note
26.5
μ
s 13.25
μ
s
0 1 1 fCLK/6 318/fCLK 39.75
μ
s
Note
19.875
μ
s 9.9375
μ
s
1 0 0 fCLK/5 265/fCLK
Setting
prohibited
33.125
μ
s
Note
16.5625
μ
s 8.28125
μ
s
1 0 1 fCLK/4 212/fCLK 53
μ
s
Note
26.5
μ
s
Note
13.25
μ
s 6.625
μ
s
1 1 0 fCLK/2 106/fCLK
Setting
prohibited
26.5
μ
s
Note
13.25
μ
s
Note
6.625
μ
s 3.3125
μ
s
1 1 1
0 1 Normal 2
fCLK/1
53 f
AD
(number
of
sampling
clock:
23 f
AD)
53/f
CLK 53
μ
s
Note
13.25
μ
s
Note
6.625
μ
s
Note
3.3125
μ
s Setting
prohibited
0 0 0 fCLK/32 2016/fCLK Setting
prohibited
63
μ
s
0 0 1 fCLK/16 1008/fCLK
Setting
prohibited
63
μ
s 31.5
μ
s
0 1 0 fCLK/8 504/fCLK 63
μ
s 31.5
μ
s 15.75
μ
s
0 1 1 fCLK/6 378/fCLK 47.25
μ
s 23.625
μ
s 11.8125
μ
s
1 0 0 fCLK/5 315/fCLK
Setting
prohibited
39.375
μ
s 19.6875
μ
s 9.84375
μ
s
1 0 1 fCLK/4 252/fCLK 63
μ
s
Note
31.5
μ
s 15.75
μ
s 7.875
μ
s
1 1 0 fCLK/2 126/fCLK
Setting
prohibited
31.5
μ
s
Note
15.75
μ
s 7.875
μ
s 3.9375
μ
s
1 1 1
1 0 Low-
voltage 1
fCLK/1
63 f
AD
(number
of
sampling
clock:
33 f
AD)
63/f
CLK 63
μ
s
Note
15.75
μ
s
Note
7.875
μ
s 3.9375
μ
s Setting
prohibited
0 0 0 fCLK/32 6944/fCLK Setting
prohibited
217
μ
s
0 0 1 fCLK/16 3472/fCLK
Setting
prohibited
217
μ
s 108.5
μ
s
0 1 0 fCLK/8 1736/fCLK 217
μ
s 108.5
μ
s 54.25
μ
s
0 1 1 fCLK/6 1302/fCLK 162.75
μ
s 81.375
μ
s 40.6875
μ
s
1 0 0 fCLK/5 1085/fCLK
Setting
prohibited
135.625
μ
s 67.8125
μ
s
33.90625
μ
s
1 0 1 fCLK/4 868/fCLK 217
μ
s 108.5
μ
s 54.25
μ
s 27.125
μ
s
1 1 0 fCLK/2 434/fCLK
Setting
prohibited
108.5
μ
s 54.25
μ
s 27.125
μ
s 13.5625
μ
s
1 1 1
1 1 Low-
voltage 2
fCLK/1
217 f
AD
(number
of
sampling
clock:
187 f
AD)
217/f
CLK 217
μ
s 54.25
μ
s 27.125
μ
s 13.5625
μ
s Setting
prohibited
Note When using ANI16 to ANI30, setting this value is prohibited.
(Cautions and Remark are listed on the next page.)
<R>