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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 529
Jul 04, 2013
Caution If the SSECm bit is 1, the PEFm1, FEFm1, and OVFm1 flags are not set when a parity error,
framing error, or overrun error occurs and no error interrupt (INTSREq) is generated. Therefore,
when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag before setting
the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9
bits).
Remarks 1. <1> to <9> in the figure correspond to <1> to <9> in Figure 12-92 Timing Chart of SNOOZE Mode
Operation (EOCm1 = 1, SSECm = 1).
2. m = 0; q = 0, n = 0 to 3
<R>