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RL78/G1A CHAPTER 15 DMA CONTROLLER
Figure 15-4. Format of DMA Mode Control Register n (DMCn) (2/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 0
DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0
(When n = 0 or 1)
Selection of DMA start source
Note
IFCn
3
IFCn
2
IFCn
1
IFCn
0
Trigger signal Trigger contents
0 0 0 0
−
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
0 0 0 1 INTAD A/D conversion end interrupt
0 0 1 0 INTTM00 End of timer channel 0 count or capture
end interrupt
0 0 1 1 INTTM01 End of timer channel 1 count or capture
end interrupt
0 1 0 0 INTTM02 End of timer channel 2 count or capture
end interrupt
0 1 0 1 INTTM03 End of timer channel 3 count or capture
end interrupt
0 1 1 0 INTST0/INTCSI00
UART0 transmission transfer end or
buffer empty interrupt/CSI00 transfer end
or buffer empty interrupt
0 1 1 1 INTSR0/INTCSI01
UART0 reception transfer end
interrupt/CSI01 transfer end or buffer
empty interrupt
1 0 0 0 INTST1/INTCSI10
UART1 transmission transfer end or
buffer empty interrupt/CSI10 transfer end
or buffer empty interrupt
1 0 0 1 INTSR1/INTCSI11
UART1 reception transfer end
interrupt/CSI11 transfer end or buffer
empty interrupt
1 0 1 0 INTST2/INTCSI20
UART2 transmission transfer end or
buffer empty interrupt/CSI20 transfer end
or buffer empty interrupt
1
UART2 reception transfer end
interrupt/CSI21 transfer end or buffer
empty interrupt
0 1 1 INTSR2/INTCSI21
Other than above Setting prohibited
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
Remark n: DMA channel number (n = 0, 1)
R01UH0305EJ0200 Rev.2.00 673
Jul 04, 2013