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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 261
Jul 04, 2013
Figure 6-57. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Interrupt signal
(INTTMmn)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
Note
CKm0
CKm1
Edge
detection
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
TImn pin
Noise
filter
TNFENxx
Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 6-58. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TSmn
TEmn
TImn
TDRmn
TCRmn
b
0000H
a
c
INTTMmn
FFFFH
b
a
c
OVF
0000H
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output
pin (TOmn) : n = 0, 1, 3 to 7))
2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TImn: TImn pin input signal
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
OVF: Bit 0 of timer status register mn (TSRmn)
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