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RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
Operation clock
Counter Undefined
<1> <2> <3> <4> <5> <6>
<7>
<9>, <10> <11>, <12>
<8>
<8>
MDAH,
MDAL
0000H
008CH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0006H
XXXXH
XXXXH
0000H
0230H
0000H
08C0H
0000H
2300H
0000H
8C00H
0002H
3000H
0008H
C000H
0023H
0000H
008CH
0000H
0230H
0000H
08C0H
0000H
2300H
0000H
8C00H
0000H
3000H
0000H
C000H
0001H
0000H
0002H
0000H
0005H
0000H
0005H
MDUC
DIVST
INTMD
MDBH,
MDBL
XXXXH
XXXXH
MDCH,
MDCL
XXXXH
XXXXH
1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH0H 0H
80H 80H81H
0000H
0023H
Figure 14-10. Timing Diagram of Division Operation (Example: 35 ÷ 6 = 5, Remainder 5)
R01UH0305EJ0200 Rev.2.00 667
Jul 04, 2013