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RL78/G1A CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00 393
Jul 04, 2013
Figure 11-37. Flowchart for Setting up SNOOZE Mode
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Start of setup
The A/D conversion
operations are performed.
End of A/D conversion
INTAD
generation
Yes
No
AWC = 0
The ports are set to analog input.
ANI0 to ANI12 pins: Set using the ADPC register
ANI16 to ANI30 pins: Set using the PMCx register
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode.
ADSCM bit: One-shot conversion mode
ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage.
ADRCK bit: This is used to select the range for the A/D conversion result comparison value
generated by the interrupt signal from AREA1, AREA3, and AREA2.
ADTYP bit: 8-bit/12-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result comparison values.
• ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
The ports are set to the input mode.
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register
setting
• ADS register setting
(The order of the settings
is irrelevant.)
ADPC and PMCx
register settings
PER0 register setting
Reference voltage
stabilization wait time count A
AWC = 1
ADCE bit setting
The reference voltage stabilization wait time count A indicated by A below may be required if the
values of the ADREFP1 and ADREFP0 bits are changed.
If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 10 μs
A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1,
respectively: A = 1 μs
Immediately before entering the STOP mode, enable the SNOOZE mode by setting the AWC bit of
the ADM2 register to 1.
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
After hardware trigger is generated, the system automatically counts up to the stabilization
wait time for A/D power supply and A/D conversion is started in the SNOOZE mode.
The clock request signal
(an internal signal) is
automatically set to the low
level in the SNOOZE mode.
The conversion results are stored in the ADCR and ADCRH registers.
Storage of conversion
results in the ADCR and
ADCRH registers
Enter the STOP mode
Normal
operation
Hardware trigger
generation
STOP
mode
SNOOZE
mode
Normal
operation
Normal operation
The A/D conversion end interrupt (INTAD) is generated.
Note 1
Release the SNOOZE mode by clearing the AWC bit of the ADM2 register to 0.
Note 2
PMx register setting
• ADM0 register setting
Notes 1. If the A/D conversion end interrupt request signal (INTAD) is not generated by setting ADRCK bit and
ADUL/ADLL register, the result is not stored in the ADCR and ADCRH registers. The system enters the
STOP mode again. If a hardware trigger is input later, A/D conversion operation is again performed in the
SNOOZE mode.
2. If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or
normal operation mode. Be sure to clear the AWC bit to 0.
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