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RL78/G1A CHAPTER 21 VOLTAGE DETECTOR
21.5 Cautions for Voltage Detector
(1) Voltage fluctuation when power is supplied <R>
In a system where the supply voltage (V
DD) fluctuates for a certain period in the vicinity of the LVD detection
voltage, the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following
action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
<R>
Figure 21-9. Example of Software Processing If Supply Voltage Fluctuation Is 50 ms or Less in Vicinity of LVD
Detection Voltage
See Figure 19-5 Procedure for Checking Reset Resource.
Note 1
Reset
Initialization
processing <1>
50 ms have passed?
(TMIFmn = 1?)
Initialization
processing <2>
Setting timer array unit
(to measure 50 ms)
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Yes
No
Clearing WDT
; e.g. f
CLK
= High-speed on-chip oscillator clock (4.04 MHz (MAX.))
Source: f
MCK
= (4.04 MHz (MAX.))/2
8
,
where comparison value = 789: ≅ 50 ms
Timer starts (TSmn = 1).
Note If reset is generated again during this period, initialization processing <2> is not started.
Remark m = 0
n = 0 to 7
R01UH0305EJ0200 Rev.2.00 770
Jul 04, 2013