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RL78/G1A CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00 380
Jul 04, 2013
11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
hardware trigger standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts. (At this time, no hardware trigger is necessary.)
<4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-25. Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
Operation Timing
ADCE is set to 1.
<1>
A hardware trigger
is generated.
<2>
A hardware trigger is
generated during A/D
conversion operation.
<4>
A/D conversion ends
and the next
conversion
starts.
<3>
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
<5>
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Conversion is
interrupted and
restarts.
<3> <3> <3>
<3>
ADCS is overwritten
with 1 during A/D
conversion operation.
<6>
ADCS is cleared
to 0 during A/D
conversion operation.
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
Stop status
ANI0 ANI1
The trigger
is not
acknowledged.
Trigger
standby
status
Trigger
standby
status
The trigger
is not
acknowledged.
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI0)
Data 4
(ANI0)
Data 2
(ANI0)
Data 3
(ANI0)
Data 4
(ANI0)
Data 5
(ANI0)
Data 6
(ANI1)
Data 6
(ANI1)
Data 8
(ANI1)
Data 7
(ANI1)
Data 8
(ANI1)
Data 9
(ANI1)
Stop status
Conversion is
interrupted.
<7>