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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 522
Jul 04, 2013
12.6.3 SNOOZE mode function
The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP
mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the
UART to perform reception operations without CPU operation. Only UART0 channel can be set to the SNOOZE mode.
When using UARTq in the SNOOZE mode, perform the following steps before entering the STOP mode. (See Figure 12-
92 Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) and Figure 12-94
Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1).)
• In the SNOOZE mode, the baud rate setting for UART reception needs to be changed to a value different from that in
normal operation. Set the SPSm register and bits 15 to 9 of the SDRmn register with reference to Table 12-3.
• Set the EOCmn and SSECmn bits. This is for enabling or stopping generation of an error interrupt (INTSRE0) when a
communication error occurs.
• Set the SWCm bit of serial standby control register m (SSCm) to 1 immediately before entering the STOP mode.
After initial setup finishes, set the SSm1 bit of serial channel start register m (SSm) to 1, which sets the SEm1 bit to 1.
If edge of RxDq is detection after switching to the STOP mode, the UART reception is started.
Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock (f
IH) is
selected for fCLK.
2. The maximum transfer rate when using UARTq in the SNOOZE mode is 4800 bps.
3. When SWCm = 1, UARTq can be used only when the reception operation is started in the STOP
mode. When used simultaneously with another SNOOZE mode function or interrupt, if the
reception operation is started in a state other than the STOP mode, such as those given below,
data may not be received correctly and a framing error or parity error may be generated.
• When after the SWCm bit has been set to 1, the reception operation is started before the STOP
mode is entered
• When the reception operation is started while another function is in the SNOOZE mode
• When after returning from the STOP mode to normal operation due to an interrupt or other
cause, the reception operation is started before the SWCm bit is returned to 0
4. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFmn,
FEFmn, or OVFmn flag is not set and an error interrupt (INTSREq) is not generated. Therefore,
when the setting of SSECm = 1 is made, clear the PEFmn, FEFmn, or OVFmn flag before setting
the SWC0 bit to 1 and read the value in bits 7 to 0 (RxDq register) of the SDRm1 register.
Remark m = 0; q = 0
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