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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 263
Jul 04, 2013
Figure 6-60. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel
default
setting
Sets corresponding bit of noise filter enable register 1
(NFEN1) to 0 (OFF) or 1 (ON).
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Clears the TOEmn bit to 0 and stops operation of TOmn.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets the TSmn bit to 1.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
TEmn = 1, and the TImn pin start edge detection wait
status is set.
Operation
start
Detects the TImn pin input count start valid edge.
Clears timer count register mn (TCRmn) to 0000H and
starts counting up.
During
operation
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TMRmn register, TOMmn, TOLmn,
TOmn, and TOEmn bits cannot be changed.
When the TImn pin start edge is detected, the counter
(TCRmn) counts up from 0000H. If a capture edge of the
TImn pin is detected, the count value is transferred to
timer data register mn (TDRmn) and INTTMmn is
generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared. The TCRmn register stops
the count operation until the next TImn pin start edge is
detected.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
The OVF bit of the TSRmn register is also held.
TAU
stop
The TAUmEN bit of the PER0 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin
(TOmn) : n = 0, 1, 3 to 7))
Operation is resumed.
<R>