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RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION
17.3.2 Key return mode registers 0, 1 (KRM0, KRM1)
These registers set the key interrupt mode.
The KRM0 and KRM1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
Figure 17-3. Format of Key Return Mode Registers 0, 1 (KRM0, KRM1)
Address: FFF37H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
KRM0 KRM07 KRM06 KRM05 KRM04 KRM03 KRM02 KRM01 KRM00
Address: FFF36H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
KRM1 0 0 0 0 0 0 KRM09 KRM08
KRM0n Key interrupt mode control
0 Does not detect key interrupt signal
1 Detects key interrupt signal
Cautions 1. The on-chip pull-up resistors can be applied by setting the corresponding key interrupt input
pins (bits) in pull-up resistor registers 0, 1, 7, and 12 (PU0, PU1, PU7, PU12) to 1.
2. An interrupt will be generated if the target bit of the KRM0, KRM1 registers are set while a low
level (when KREG = 0)/high level (when KREG = 1) is being input to the key interrupt input pin.
To ignore this interrupt, set the KRM0, KRM1 registers after disabling interrupt servicing by using
the interrupt mask flag. Afterward, clear the interrupt request flag and enable interrupt servicing
after waiting for the key interrupt input high-level width/low-level width (see 29.4 AC
Characteristics and 30.4 AC Characteristics).
3. The pins not used in the key interrupt mode can be used as normal ports.
Remarks 1. n = 0 to 9
2. (KR0 to KR3): 25-pin products
KR0 (KR0 to KR5): 32-pin products
KR0 to KR5: 48-pin products
KR0 to KR9: 64-pin products
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01UH0305EJ0200 Rev.2.00 718
Jul 04, 2013