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RL78/G1A CHAPTER 15 DMA CONTROLLER
15.2 Configuration of DMA Controller
The DMA controller includes the following hardware.
Table 15-1. Configuration of DMA Controller
Item Configuration
Address registers
• DMA SFR address registers 0, 1 (DSA0, DSA1)
• DMA RAM address registers 0, 1 (DRA0, DRA1)
Count register • DMA byte count registers 0, 1 (DBC0, DBC1)
Control registers
• DMA mode control registers 0, 1 (DMC0, DMC1)
• DMA operation control register 0, 1 (DRC0, DRC1)
15.2.1 DMA SFR address register n (DSAn)
This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA channel n.
Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH.
This register is not automatically incremented but fixed to a specific value.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DSAn register can be read or written in 8-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 00H.
Figure 15-1. Format of DMA SFR Address Register n (DSAn)
Address: FFFB0H (DSA0), FFFB1H (DSA1) After reset: 00H R/W
7 6 5 4 3 2 1 0
DSAn
Remark n: DMA channel number (n = 0, 1)
R01UH0305EJ0200 Rev.2.00 669
Jul 04, 2013