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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 192
Jul 04, 2013
Figure 6-4. Internal Block Diagram of Channel 5 of Timer Array Unit 0
Count clock
selection
TO05
PMxx
CKS050
CCS05STS052STS051 STS050 MD052CIS051CIS050 MD053 MD051MD050
OVF
05
INTTM05
(Timer interrupt)
CK00
CK01
fMCK
fTCLK
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 05 (TSR05)
Overflow
Timer data register 05 (TDR05)
Timer counter register 05 (TCR05)
Timer mode register 05 (TMR05)
Channel 5
Timer controller
Mode
selection
Edge
detection
Interrupt signal from master channel
Trigger
selection
Count clock
selection
Operating
clock selection
CKS051
TIS01 TIS00
fSUB
fIL
TI05
Timer input select
register 0 (TIS0)
TIS02
Selector
Figure 6-5. Internal Block Diagram of Channel 7 of Timer Array Unit 0
TO07
PMxx
CKS070
CCS07STS072STS071 STS070 MD072CIS071CIS070 MD073 MD071MD070
OVF
07
INTTM07
(Timer interrupt)
CK00
CK01
f
MCK
f
TCLK
TI07
ISC1
RxD2
Input switch
control register
(ISC)
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 07 (TSR07)
Overflow
Timer data register 07 (TDR07)
Timer counter register 07 (TCR07)
Timer mode register 07 (TMR07)
Timer controller
Mode
selection
Edge
detection
Interrupt signal from master channel
Channel 7
Trigger
selection
Count clock
selection
Operating
clock selection
Selector
CKS071