Filter
Top Products
RL78/G1A CHAPTER 5 CLOCK GENERATOR
R01UH0305EJ0200 Rev.2.00 171
Jul 04, 2013
Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/5)
(6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
HIOSTOP
Oscillation accuracy
stabilization time
MCM0
(C) → (B) 0 18
μ
s to 65
μ
s 0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
Remark The oscillation accuracy stabilization time changes according to the temperature conditions and the STOP
mode period.
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
XTSTOP
Waiting for Oscillation
Stabilization
CSS
(C) → (D) 0 Necessary 1
Unnecessary if the CPU is operating with the
subsystem clock
(8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
HIOSTOP
Oscillation accuracy
stabilization time
CSS
(D) → (B) 0 18
μ
s to 65
μ
s 0
Unnecessary if the CPU is operating with the high-
speed on-chip oscillator clock
Remarks 1. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15.
2. The oscillation accuracy stabilization time changes according to the temperature conditions and the
STOP mode period.
<R>
<R>