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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 250
Jul 04, 2013
Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (2/2)
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0
0: Sets master channel output mode.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin
(TOmn) : n = 0, 1, 3 to 7))